The field of the invention is that of embedding MRAM memories or similar structures in the back end of logic or general purpose integrated circuits.
The field of MRAM (Magnetic memory Random Access Memory) circuits is growing rapidly, aided by the relevant considerations that MRAM is non-volatile, and promises low power consumption, high speed, and high packing density. MRAM has the considerable practical advantage that it can be implemented in the Back End of the Line (BEOL), but there remains a difficulty with the-requirements of the wiring in the BEOL. Conventional BEOL wiring schemes require that the wiring layers be spaced apart vertically to reduce capacitance and therefore permit high speed switching. MRAM devices, however, have a need for close spacing vertically between the wiring and the magnetic layers that form the MRAM cell in order to reduce the amount of current needed flip the magnetization state from one direction to the other.
The spacing needed for best performance of MRAM cells is considerably less than that needed in order to optimize capacitance and operation speed in logic circuits.
Various schemes have been proposed to move the MRAM cells away from the logic interconnect areas, but they require extra wiring layers or otherwise increase costs.
The art thus has a need for a geometrically compact configuration that places MRAM cells in close proximity to logic wiring, but still maintains the separate requirements of logic and MRAM.
The invention relates to a circuit configuration in which structures such as MRAM cells are placed in the upper regions (BEOL) of an integrated circuit while simultaneously maintaining the dimensions needed for the structure and also for good operation of the logic circuit.
A feature of the invention is the placement of an MRAM cell within an interlevel dielectric in the back end.
Another feature of the invention is the simultaneous satisfaction of the spacing requirements of the logic back end wiring and of the MRAM cell.
Another feature of the invention is etching a dual damascene aperture to a standard depth for logic wiring and etching an aperture to a deeper depth for the other structure.